System and method for generating two effective frequencies using a single clock

ABSTRACT

A method and apparatus are disclosed for generating a second clock signal, having a second effective clock frequency, from a first clock signal, having a first effective clock frequency. Clock pulses of the first clock signal are counted to generate a count value. When the count value reaches a predetermined blanking value, a blanking signal is generated. The blanking signal blanks at least one clock pulse of the first clock signal. The process is repeated multiple times at a predetermined rate corresponding to the predetermined blanking value to generate the second clock signal.

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

U.S. Pat. No. 6,424,194, U.S. application Ser. No. 09/540,243 filed onMar. 31, 2000, U.S. Pat. Nos. 6,389,092, 6,340,899, U.S. applicationSer. No. 09/919,636 filed on Jul. 31, 2001, U.S. application Ser. No.09/860,284 filed on May 18, 2001, U.S. application Ser. No. 10/028,806filed on Oct. 25, 2001, U.S. application Ser. No. 09/969,837 filed onOct. 1, 2001, U.S. application Ser. No. 10/159,788 entitled “PhaseAdjustment in High Speed CDR Using Current DAC” filed on May 30, 2002,U.S. application Ser. No. 10/179,735 entitled “Universal Single-EndedParallel Bus; fka, Using 1.8V Power Supply in 0.13 MM CMOS” filed onJun. 21, 2002, and application Ser. No. 10/340,408 filed on Jan. 10,2003, are each incorporated herein by reference in their entirety.

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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SEQUENCE LISTING

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MICROFICHE/COPYRIGHT REFERENCE

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BACKGROUND OF THE INVENTION

Embodiments of the present invention relate generally to a method andapparatus for generating clock signals in a high-speed digitaltransceiver, and more particularly to generating a second clock signalfrom a first clock signal.

High-speed digital communication networks over copper and optical fiberare used in many network communication and digital storage applications.Ethernet and Fibre Channel are two widely used communication protocolsused today and continue to evolve to respond to the increasing need forhigher bandwidth in digital communication systems.

The Open Systems Interconnection (OSI) model (ISO standard) wasdeveloped to establish standardization for linking heterogeneouscomputer and communication systems. The OSI model includes sevendistinct functional layers including Layer 7: an application layer;Layer 6: a presentation layer; Layer 5: a session layer; Layer 4: atransport layer; Layer 3: a network layer; Layer 2: a data link layer;and Layer 1: a physical layer. Each OSI layer is responsible forestablishing what is to be done at that layer of the network but not howto implement it.

Layers 1 to 4 handle network control and data transmission andreception. Layers 5 to 7 handle application issues. Specific functionsof each layer may vary to a certain extent, depending on the exactrequirements of a given protocol to be implemented for the layer. Forexample, the Ethernet protocol provides collision detection and carriersensing in the data link layer.

The physical layer, Layer 1, is responsible for handling all electrical,optical, and mechanical requirements for interfacing to thecommunication media. The physical layer provides encoding and decoding,synchronization, clock data recovery, and transmission and reception ofbit streams. Typically, high-speed electrical or optical transceiversare the hardware elements used to implement this layer.

As data rate and bandwidth requirements increase, 10 Gigabit datatransmission rates are being developed and implemented in high-speednetworks. There is much pressure to develop a 10 Gigabit physical layerfor high-speed serial data applications.

In the physical layer, several sublayers are supported. As an example,for 10 Gigabit serial operation, some of the key sublayers include a PMDTX/RX (physical media dependent transmit and receive) sublayer, a PMDPCS (physical media dependent physical encoding) sublayer, a XGXS PCS(10 Gigabit media independent interface extender physical encoding)sublayer, and a XAUI TX/RX (10 Gigabit attachment unit interfacetransmit and receive) sublayer.

An optical-based transceiver, for example, includes various functionalcomponents such as clock data recovery, clock multiplication,serialization/de-serialization, encoding/decoding, electrical/opticalconversion, descrambling, controlling, and data storage.

Certain functional components within an optical-based transceiver mayrequire clock signals having slightly different effective clockfrequencies. For example, a clock data recovery (CDR) circuit and asynchronizer/descrambler/decoder circuit may require slightly differenteffective clock frequencies in an optical-based transceiver. Typically,the clock signals are generated independently of each other, or oneclock signal is multiplied up and then divided down by large ratios toachieve a second clock signal. Such methods require significantadditional hardware than that required for generating a single originalclock signal.

Further limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of skill in the art, throughcomparison of such systems with the present invention as set forth inthe remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

Certain embodiments of the present invention provide a method andapparatus for generating a second clock signal from a first clock signalwhere the effective clock frequencies of the two clock signals differslightly.

A method of the present invention provides for generating a second clocksignal, having a second effective clock frequency, from a first clocksignal, having a first effective clock frequency. Clock pulses of thefirst clock signal are counted to generate a count value. When the countvalue reaches a predetermined blanking value, a blanking signal isgenerated. The blanking signal blanks at least one clock pulse of thefirst clock signal. The process is repeated multiple times at apredetermined rate corresponding to the predetermined blanking value togenerate the second clock signal.

Apparatus of the present invention includes a clock source generating afirst clock signal and a modulo counter, counting clock pulses of thefirst clock signal and generating a mod signal when the modulo counterreaches a predetermined blanking value. An inverter generates a blankingsignal in response to the mod signal and a logic circuit generates asecond clock signal in response to the first clock signal and theblanking signal.

These and other advantages, aspects and novel features of the presentinvention, as well as details of an illustrated embodiment thereof, willbe more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a top-level block diagram of an optical-based transceiver chipin accordance with an embodiment of the present invention.

FIG. 2 is a more detailed schematic block diagram of the optical-basedtransceiver chip of FIG. 1 in accordance with an embodiment of thepresent invention.

FIG. 3 is a schematic block diagram of an apparatus within theoptical-based transceiver chip of FIG. 2 to generate a second clocksignal from a first clock signal in accordance with an embodiment of thepresent invention.

FIG. 4 is flowchart of a method to generate a second clock signal from afirst clock signal using the apparatus of FIG. 3 in accordance with anembodiment of the present invention.

FIG. 5 is a timing diagram of the first clock signal and the secondclock signal with a blanked pulse (gap) in accordance with an embodimentof the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a top-level block diagram of an optical-based transceiver chip1 in accordance with an embodiment of the present invention. The PMDTX/RX sublayer 220 (physical media dependent transmit and receivesublayer) provides the electrical functionality for transmission andreception of 10 Gigabit serial data. The functionality includes clockmultiplication and data serialization, clock data recovery and datade-serialization, signal amplification and equalization, anddifferential signal driving.

The PMD PCS sublayer 240 (physical media dependent physical encodingsublayer) is responsible for coding data to be transmitted and decodingdata to be received on the PMD side of the transceiver. Thefunctionality includes 64B/66B synchronization, descrambling, anddecoding, 64B/66B encoding and scrambling, data transitioning,multiplexing, and phase detecting.

The XGXS PCS sublayer 230 (10 Gigabit media independent interfaceextender physical encoding sublayer) is responsible for coding data tobe transmitted and decoding data to be received on the XAUI side of thetransceiver. The functionality includes 8B/10B encoding, 8B/10Bdecoding, randomizing, and lane alignment.

The XAUI TX/RX sublayer 210 (10 Gigabit attachment unit interfacetransmit and receive sublayer) provides the electrical functionality fortransmission and reception of 3 Gigabit 4-channel serial data. Thefunctionality includes clock multiplication and data serialization,clock data recovery and data de-serialization, signal amplification, anddifferential signal driving.

FIG. 2 is a more detailed schematic block diagram of the optical-basedtransceiver chip 1 of FIG. 1 in accordance with an embodiment of thepresent invention. The optical-based transceiver chip 1 comprises threemain blocks including a transmit block 310, a receive block 340, and amanagement and control block 370. Clock interfaces are provided forconfiguring the XAUI and PMD interfaces to asynchronous or independentasynchronous operations in accordance with an embodiment of the presentinvention.

The receiver block 340 accepts 10 Gigabit serial PMD data and reformatsthe data for transmission on the 4-lane 3 Gigabit XAUI transmitters 362.One of the 3 Gigabit CMU clocks in the XAUI TX/RX sublayer 210 is usedto retime all four XAUI transmitters. The XAUI CMU 346 in the XAUI TX/RXsublayer 210 is phase-locked to an external reference clock.

The PMD clock and data recovery (CDR)/Deserializer 348 within the PMDTX/RX sublayer 220 generates a clock that is at the same frequency asthe incoming data bit rate (10 Gigabit data rate) at the serial datainputs, PDIP/N 344. The clock is phase-aligned by a PLL so that itsamples the data in the center of the data eye pattern in accordancewith an embodiment of the present invention.

The phase relationship between the edge transitions of the data andthose of the generated clock are compared by a phase/frequencydiscriminator. Output pulses from the discriminator indicate thedirection of phase corrections.

The output of the loop filter controls the frequency of the VCO, whichgenerates the recovered clock. Frequency stability without incoming datais guaranteed by an internal reference clock that the PLL locks ontowhen data is lost.

The transceiver chip 1 includes a lock detect circuit that monitors the10 Gigabit frequency of the internal VCO within the PMD TX/RX sublayer220. The frequency of the incoming data stream is within ±100 ppm of the10 Gigabit data stream for the lock detector to declare signal lock. Thelock detect status is observable in the Analog Transceiver StatusRegister 0. P_LKDTCBR goes high when the PMD CDR/Deserializer 348 islocked to the incoming data. The CDR lock detect signal is also providedas an output status at the PCDRLK pin 348A.

The PMD serial data stream is deserialized by a serial-to-parallelconverter of CDR/Deserializer 348 in the PMD TX/RX sublayer 220. The CDRoutput clocks the serial-to-parallel converter. Under normal operation,the CDR recovers the clock from the data. If data is not present, theclock is recovered from the internal reference clock. The output is sentto the RX Gearbox 350 within PMD PCS sublayer 240.

The RX gearbox 350 in the PMD PCS sublayer 240 is a buffer that converts64-bit data to 66-bit data for more efficient parallelization. The RXgearbox 350 receives 64-bit data from the CDR/Deserializer 348 at322.265 MHz. The RX gearbox 350 outputs 66-bit data to the 64B/66BSynchronizer/Descrambler/Decoder 352 within the PMD TX/RX sublayer 220.A register bank is employed which is accessed in a circular manner.

A Frame Synchronizer (which is a part of the 64B/66BSynchronizer/Descrambler/Decoder 352 in the PMD PCS sublayer 240)searches for the 66-bit boundary of the frame data and obtains lock to66-bit blocks using the sync header and outputs 66-bit blocks. Thedescrambler (which is also a part of the 64B /66BSynchronizer/Descrambler/Decoder 352 in the PMD PCS sublayer 240)processes the payload to reverse the effect of the scrambler using thesame polynomial. The receiver process decodes blocks according to IEEE802.3ae clause 49.

The XAUI CMU 346 within the XAUI TX/RX sublayer 210 has a PLL thatgenerates the 3 Gigabit clock by multiplying the internal 156.25-MHzreference clock in accordance with an embodiment of the presentinvention. The transceiver chip 1 includes a lock detect circuit, whichmonitors the frequency of the internal VCO. The CMU lock detect bit goeshigh when the XAUI CMU PLL is locked. The lock detect status is in theAnalog Transceiver Status Register 0, bit 7.

The transceiver chip 1 supports asynchronous clocking mode operation ofthe XAUI and PMD interfaces. The local reference clock or externaltransmit VCXO may adhere to the IEEE specifications.

In the asynchronous mode, an elastic FIFO 354 is used that accommodatesa frequency difference of up to 200 ppm between a recovered clock and alocal reference clock. Both the RX and TX data paths 310 and 320 containelastic FIFOs 354 and 324. Idle columns of four bytes are inserted ordeleted during the IPG (inter packet gap) once the distance between theelastic FIFO's read and write pointers exceed a threshold. In addition,a column of sequence orders may be deleted during the IPG once thedistance between the elastic FIFO's read and write pointer exceed athreshold. The delete adjustments only occur on IPG streams that containat least two columns of idles or sequence order sets.

In an embodiment of the present invention, a 312.5 MHz clock signal isderived from a 322.26 MHz clock signal. For example, in the receiveblock 340, the CDR/Deserializer 348 generates a first clock signal at aneffective clock frequency of 322.26 MHz that is used to clock one sideof the RX gearbox 350. A second clock signal is generated within theCDR/Deserializer 348 from the first clock signal at an effectivefrequency of 312.5 MHz. The second clock signal at 312.5 MHz is used toclock another side of the RX gearbox 350, the 64B/66BSynchronizer/Descrambler/Decoder 352, and the elastic FIFO 354. Also,the second clock signal at 312.5 MHz is divided by 2 to form a 156.25MHz clock signal and may be muxed to the XAUI CMU 346.

Referring to FIG. 3, in an embodiment of the present invention, theclock generating circuit 5 may be used to generate the second clocksignal (CLK 2) from the first clock signal (CLK 1). The first clocksignal 50 at 322.26 MHz is generated by a clock source 10 withinCDR/Deserializer 348. The clock source 10 may be a circuit that derivesthe first clock signal 50 from another clock signal or may be anoriginal clock source.

A modulo counter 20 is used to count clock pulses of the first clocksignal 50 to generate a count value as described in step 410 of FIG. 4.In step 420, the modulo counter outputs a mod signal 60 to an inverter30 when the count value of the modulo counter 20 reaches a predeterminedblanking value. As a result, the inverter 30 outputs a blanking signal70 to blank at least one clock pulse of the first clock signal 50 instep 430. In step 430, the first clock signal 50 and the blanking signal70 are input to a logic gate (e.g. an AND gate) 40. The output of thelogic gate 40 is the second clock signal (CLK 23) 80.

Referring to FIG. 5, in accordance with an embodiment of the presentinvention, when the predetermined blanking value is 33, every 33^(rd)clock pulse in CLK 1 50 will be blanked creating a gap 81 in CLK 2 80.As a result, the effective clock frequency of CLK 2 80 will be 312.5 MHzas follows:[(33−1)/33]*322.26 MHz=312.5 MHz  (eqn. 1)

The transmit block 310 collects 4-lane 3 Gigabit data at the XAUIreceivers 312 and reformats the data for 10 Gigabit serial transmissionat the PMD differential CML drivers 314 in accordance with an embodimentof the present invention. The PMD CMU (clock multiplier unit)/Serializer316 in the PMD TX/RX sublayer 220 is phase-locked to an externalreference clock.

Each XAUI serial data stream is de-serialized to a 10-bit word by aserial-to-parallel converter of the DLL & Deserializer 318 within theXAUI TX/RX sublayer 210. The DLL output clocks the serial-to-parallelconverter. Under normal operation, the DLL recovers the clock from thedata. If data is not present, the clock is recovered from the internalreference clock. The output is sent to the XGXS PCS sublayer 230 in thedigital core 130.

The PMD PCS sublayer 240 uses a transmission code to improve thetransmission characteristics of information to be transferred across thelink and to support transmission of control and data characters inaccordance with an embodiment of the present invention. The 64B/66Bencoding (defined by IEEE 802.2ae clause 49 for transmission code andperformed by the 64B/66B Encoder/Scrambler 326) ensures that sufficienttransitions are present in the PHY bit stream to make clock recoverypossible at the receiver.

The TX gearbox 328 in the PMD PCS sublayer 240 is a buffer that converts66-bit data to 64-bit data for more efficient serialization. The TXgearbox 328 receives 64-bit data from the 64B/66B Encoder/Scrambler 326and a 2-bit sync from the Type Generator at 156.25 MHz. The TX gearbox328 outputs 64-bit data at 322.265 MHz to the PMD CMU/Serializer 316within the PMD TX/RX sublayer 220. A register bank is employed which isaccessed in a circular manner.

Data is read out of the TX gearbox 328 using an internally generated322.265 MHz clock. The data is converted to a 10 Gigabit serial streamwithin PMD TX/RX sublayer 220 and driven off-chip. Bit 0 of frame 0(LSB) is shifted out first.

The PMD CMU/Serializer 316 within the PMD TX/RX sublayer 220 has a PLLthat generates the 10 Gigabit clock by multiplying the internal 156.25MHz reference clock.

As another example, in the transmit block 310, the CMU/Serializer 316generates a first clock signal at an effective clock frequency of 322.26MHz that is used to clock one side of the TX gearbox 328. A second clocksignal is generated within the CMU/Serializer 316 from the first clocksignal at an effective frequency of 312.5 MHz. The second clock signalat 312.5 MHz is used to clock another side of the TX gearbox 328, the64B/66B Encoder/Scrambler 326, and the elastic FIFO 324.

In an embodiment of the present invention, the clock generating circuit5 may be similarly used, as in the receive block 340, to generate thesecond clock signal from the first clock signal according to the method400.

In other embodiments of the present invention, other clock signals atother effective clock frequencies may be generated from an originalclock signal at some first clock frequency. Embodiments of the presentinvention are not limited to any particular first clock frequency orsecond clock frequency. Also, multiple clock pulses may be blankedduring one cycle of the blanking signal to obtain a particular effectiveclock frequency for the second clock signal.

In alternative embodiments of the present invention, the clockgenerating apparatus 5 and method 400 may not be part of a transceiverchip but may, instead, be a part of some other circuitry where it isdesirable to generate a second clock signal from a first clock signal.

The various elements of the apparatus 5 may be combined or separatedaccording to various embodiments of the present invention.

In summary, certain embodiments of the present invention afford anapproach for generating a second clock signal, having a second effectiveclock frequency, from a first clock signal, having a first effectiveclock frequency by blanking clock pulses from the first clock signal atregular intervals.

While the invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the invention without departing from its scope.Therefore, it is intended that the invention not be limited to theparticular embodiment disclosed, but that the invention will include allembodiments falling within the scope of the appended claims.

1. A method to generate a second clock signal, having a second effectiveclock frequency, from a first signal, having a first effective clockfrequency, said method comprising: counting clock pulses of said firstclock signal to generate a count value; inverting the counted clockpulses; generating a blanking signal when said count value reaches aparticular blanking value; blanking at least one clock pulse of saidfirst clock signal in response to said blanking signal; repeating saidcounting, said generating, and said blanking at a particular ratecorresponding to said particular blanking value to generate said secondclock signal; using the first clock signal to clock one side of areceiver gearbox; and using the second clock signal to clock at leastone of another side of the receiver gearbox, asynchronizer/descrambler/decoder, and an elastic first in first out(FIFO).
 2. The method of claim 1 further comprising clocking at leastone digital circuit with said first clock signal and said second clocksignal.
 3. The method of claim 1 wherein said second effective clockfrequency is less than said first effective clock frequency.
 4. Themethod of claim 1 wherein said blanking comprises eliminating said atleast one clock pulse from said first clock signal.
 5. The method ofclaim 1 wherein said second effective clock frequency comprises saidfirst effective clock frequency reduced by a ratio of at least one lessthan said particular blanking value divided by said particular blankingvalue.
 6. The method according to claim 1, wherein blanking at aparticular rate comprises blanking at a predetermined rate.
 7. Themethod according to claim 1, wherein the particular blanking valuecomprises a predetermined blanking value.
 8. Apparatus to generate asecond clock signal, having a second effective clock frequency, from afirst clock signal, having a first effective clock frequency, saidapparatus comprising: a clock source generating said first clock signal;a modulo counter counting clock pulses of said first clock signal andgenerating a mod signal when said modulo counter reaches a particularblanking value; a receiver gearbox at least one of asynchronizer/descrambler/decoder, and an elastic first in first out(FIFO); an inverter to generate a blanking signal in response to saidmod signal; and a logic circuit to generate said second clock signal inresponse to said first clock signal and said blanking signal, whereinthe first clock signal is used to clock one side of the receiver gearboxand the second clock signal is used to clock at least one of anotherside of the receiver gearbox, the synchronizer/descrambler/decoder, andthe elastic first in first out (FIFO).
 9. The apparatus of claim 8wherein said modulo counter resets itself and repeats counting up tosaid particular blanking value after said mod signal is generated. 10.The apparatus of claim 8 further comprising at least one digital circuitbeing clocked by said first clock signal and said second clock signal.11. The apparatus of claim 8 wherein said second effective clockfrequency is less than said first effective clock frequency.
 12. Theapparatus of claim 8 wherein said blanking signal eliminates at leastone clock pulse from said first clock signal to generate said secondclock signal.
 13. The apparatus of claim 8 wherein said second effectiveclock frequency comprises said first effective clock frequency reducedby a ratio of at least one less than said particular blanking valuedivided by said particular blanking value.
 14. The apparatus accordingto claim 8, wherein a particular blanking value comprises apredetermined blanking value.
 15. The apparatus according to claim 8,wherein blanking is adapted to occur at a particular blanking rate. 16.A digital communication system comprising: at least one transceiverperforming at least one clock function, the at least one transceivercomprising: at least one clock generating circuit to generate a secondclock signal, having a second effective clock frequency, from a firstclock signal, having a first effective clock frequency, the clockgenerating circuit comprising: a clock source for generating the firstclock signal; a modulo counter for counting clock pulses of the firstclock signal and generating a mod signal when the modulo counter reachesa particular blanking value; a receiver gearbox; at least one of asynchronizer/descrambler/decoder, and an elastic first in first out(FIFO); an inverter for generating a blanking signal in response to themod signal; and a logic circuit for generating the second clock signalin response to the first clock signal and the blanking signal, whereinthe first clock signal is used to clock one side of the receiver gearboxand the second clock signal is used to clock at least one of anotherside of the receiver gearbox, the synchronizer/descrambler/decoder, andthe elastic first in first out (FIFO).
 17. The system of claim 16,further comprising a plurality of clock interfaces, wherein the clockinterfaces are adapted to provide asynchronous clocking operation. 18.The system of claim 16, wherein the first clock signal has an effectivefrequency of 322.28 MHz, the second clock signal has an effectivefrequency of 312.5 MHz, and wherein the second clock signal is derivedfrom the first clock signal.
 19. The system of claim 16, wherein theparticular blanking value is 33, and wherein every 33^(rd) clock pulseis blanked creating gaps in the second clock signal.
 20. The system ofclaim 16, further comprising signal transmission, wherein signaltransmission is performed via four parallel transmission channels, andwherein data transmitted via parallel signal transmission is formattedfor serial transmission in a transmit block of the transceiver.
 21. Thesystem of claim 16, further comprising a serial data stream, wherein aclocked serial-to-parallel converter is adapted to convert the serialdata stream to a parallel data stream, and wherein a serial-to-parallelconverter clock is recoverable from a voltage controlled oscillator. 22.The system of claim 16, further comprising multiple clocks generatingmultiple clock pulses, wherein the multiple clock pulses are blankedduring one cycle of the blanking signal.
 23. The system of claim 16,further comprising multiple clocks adapted to generate multiple clocksignals from the first clock signal, and wherein the multiple clocksignals comprise multiple effective clock frequencies which aredifferent from an effective clock frequency of the first clock signal.24. The system of claim 16, wherein the first clock signal is adapted toclock one side of a receiver gearbox in the transceiver and the secondclock signal is adapted to cooperatively clock another side of thereceiver gearbox in the transceiver.
 25. The system of claim 16, whereinthe second effective clock frequency is less than the first effectiveclock frequency.
 26. The apparatus of claim 15, wherein the particularblanking rate comprises a predetermined blanking rate.
 27. The system ofclaim 16, wherein the particular blanking value comprises apredetermined blanking value.
 28. The system according to claim 16,wherein blanking is adapted to occur at a blanking rate.
 29. The systemof claim 28, wherein the particular blanking rate comprises apredetermined blanking rate.